Chung K. Cheng
Professor, Computer Science and Engineering
ECE Adjunct Professor, Electrical and Computer Engineering
Computer-aided design, VLSI layout automation, circuit partitioning, network flow optimization, physical design of multichip modules for hybrid package. Professor Cheng's research interests include network optimization and design automation on microelectronic circuits. He works in the area of circuit design of systems-on-chip that require integration of systems in ever-smaller dimensions. Cheng focuses on circuit analysis and floorplanning (the layout of the chip), including field programmable components, interconnect architectures, and adaptive data path modules. For circuit analysis, Cheng develops efficient methods to model and check the signal integrity of huge networks. This includes establishing circuit design guidelines that minimize crosstalk and power-supply fluctuations, while at the same time balancing delay and the amount of ringing.Floorplan optimization is considered to be one pivotal step in the deep submicron design methodology. Cheng's research on this topic aims to provide very high return toward achieving parity between technology capability and design productivity. His research team studies interconnect architecture, performance-driven layout planning, and adaptive data path modules, which constitute critical ingredients of system on chip designs.
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